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DTSTAMP:20260522T162634Z
LOCATION:Bldg. 6 - Room 104
DTSTART;TZID=Europe/Stockholm:20260701T120000
DTEND;TZID=Europe/Stockholm:20260701T123000
UID:submissions.pasc-conference.org_PASC26_sess177_pap120@linklings.com
SUMMARY:Serverless Computing for Life-Critical Science: Design Patterns an
 d Co-Design Insights from a Real-Time Earthquake Loss Alert System
DESCRIPTION:Michel Speiser (ICES Foundation)\n\nUrgent scientific computin
 g for disaster response requires both sub-minute latency and constant avai
 lability, yet traditional always-on infrastructure is uneconomical for rar
 e, unpredictable events. We present a serverless architecture for real-tim
 e earthquake loss estimation that achieves 2-minute end-to-end alerts whil
 e remaining idle 99.99% of the time. Our system, deployed as QLARM version
  4 within the Horizon Europe project GOBEYOND, demonstrates that serverles
 s computing can meet the demands of latency-critical scientific workflows 
 while maintaining pay-per-use economics.\n\nWe identify four design patter
 ns that emerged from adapting urgent earthquake loss estimation to serverl
 ess constraints: custom orchestration for workflow coordination, selective
  containerization that balances startup time with computational capability
 , warm-up strategies to mitigate cold starts, and infrastructure-as-code (
 IaC) for reproducibility and auditability. Performance measurements show o
 ver 100x speedup for large earthquakes compared to the previous generation
 , with calculation times ranging from 6 seconds for small events to 22 sec
 onds for major disasters affecting thousands of settlements. We include an
  ongoing investigation on workload partitioning for further latency reduct
 ion.\n\nOur experience reveals both strengths and limitations of serverles
 s for scientific computing. Pay-per-use economics and IaC prove well-suite
 d to urgent computing, while opaque container lifecycle management and coa
 rse resource allocation present challenges. We discuss these findings as p
 otential insights for HPC co-design, particularly for systems requiring in
 stant availability with minimal idle costs.\n\nSession Chair: Aldas Lenkša
 s (Politecnico di Milano)\n\n
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